example11-18.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY encoder IS
  GENERIC (delay: TIME);
  PORT (in1 : IN Std_Logic_Vector (7 DOWNTO 0);
        out1 : OUT Std_Logic_Vector (2 DOWNTO 0));
END encoder;
ARCHITECTURE arc_df OF encoder IS
BEGIN
  out1 <= "000" AFTER delay WHEN in1(0) = '1' ELSE
          "001" AFTER delay WHEN in1(1) = '1' ELSE
          "010" AFTER delay WHEN in1(2) = '1' ELSE
          "011" AFTER delay WHEN in1(3) = '1' ELSE
          "100" AFTER delay WHEN in1(4) = '1' ELSE
          "101" AFTER delay WHEN in1(5) = '1' ELSE
          "110" AFTER delay WHEN in1(6) = '1' ELSE
          "111" AFTER delay WHEN in1(7) = '1';
END arc_df;