example11-29.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY alu_bit IS
  PORT (op1, op2 : IN Std_Logic;
        y : IN Std_Logic_Vector (3 DOWNTO 0);
        carry_in : IN Std_Logic;
        l_xaomd : IN Std_Logic;
        sum : OUT Std_Logic;
        carry_out : BUFFER Std_Logic);
END alu_bit;
ARCHITECTURE arc_df OF alu_bit IS
  COMPONENT mux4_1
    PORT (a, b : IN Std_Logic;
          y : IN Std_Logic_Vector (3 DOWNTO 0);
          f : OUT Std_Logic);
  END COMPONENT;
  COMPONENT manchester_chain
    PORT (carry_in : IN Std_Logic;
          kill, propagate : IN Std_Logic;
          l_xaomd : IN Std_Logic;
          carry_out : BUFFER Std_Logic);
  END COMPONENT;
  SIGNAL half, q : Std_Logic;
  SIGNAL kill : Std_Logic;
BEGIN
  U1 : mux4_1 PORT MAP (op1, op2, y, q);
  U2 : Manchester_chain PORT MAP (carry_in, kill, half, l_xaomd, carry_out);
  half <= NOT q;
  kill <= (NOT op2) AND (NOT half);
  sum <= half XOR carry_in;
END arc_df;