example18-1.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY counter IS
	PORT (
		clk: IN std_logic;
		reset: IN std_logic;
		ce: IN std_logic;
		dir: IN std_logic;
		count: INOUT std_logic_vector(3 downto 0)
		);
END counter;

ARCHITECTURE behavioral OF counter IS
BEGIN
	PROCESS(clk,reset)
	BEGIN
		IF reset='1' THEN
			count<="0000";
		ELSIF clk'EVENT and clk='1' THEN
			IF ce='1' THEN
				IF dir='1' THEN
					count<=count+1;
				ELSE
					count<=count-1;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END behavioral;