example13-8.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY state_onehot IS
	PORT (
		x: IN std_logic;
		clk: IN std_logic;
		q: OUT std_logic
		);
END  state_onehot;

ARCHITECTURE behave OF state_onehot IS
	SUBTYPE STATE_TYPE IS std_logic_vector(3 downto 0);
	SIGNAL current_state:STATE_TYPE;
	SIGNAL next_state:STATE_TYPE;  
BEGIN
	combination:PROCESS(current_state,x)
	BEGIN
		CASE current_state IS
			WHEN "0001"=>--S0
			IF x='0' THEN
				q<='0';
				next_state<="0000";
			ELSE
				q<='0';
				next_state<="0010";
			END IF;
			WHEN "0010"=>--S1
			IF x='0' THEN
				q<='0';
				next_state<="0010";
			ELSE
				q<='0';
				next_state<="0100";
			END IF;
			WHEN "0100"=>--S2
			IF x='0' THEN
				q<='0';
				next_state<="0100";
			ELSE
				q<='0';
				next_state<="1000";
			END IF;
			WHEN "1000"=>--S3
			IF x='0' THEN
				q<='0';
				next_state<="1000";
			ELSE
				q<='1';
				next_state<="0001";
			END IF;
			WHEN others=>NULL;
		END CASE;
	END PROCESS;
	synchronous:PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			next_state<=current_state;
		END IF;
	END PROCESS;	
END behave;