example13-7.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY state_combination IS
	PORT (
		x: IN std_logic;
		clk: IN std_logic;
		q: OUT std_logic
		);
END  state_combination;

ARCHITECTURE behave OF state_combination IS
	SUBTYPE STATE_TYPE IS std_logic_vector(1 downto 0);
	SIGNAL current_state:STATE_TYPE;
	SIGNAL next_state:STATE_TYPE;  
BEGIN
	combination:PROCESS(current_state,x)
	BEGIN
		CASE current_state IS
			WHEN "00"=>--S0
			IF x='0' THEN
				q<='0';
				next_state<="00";
			ELSE
				q<='0';
				next_state<="01";
			END IF;
			WHEN "01"=>--S1
			IF x='0' THEN
				q<='0';
				next_state<="01";
			ELSE
				q<='0';
				next_state<="10";
			END IF;
			WHEN "10"=>--S2
			IF x='0' THEN
				q<='0';
				next_state<="10";
			ELSE
				q<='0';
				next_state<="11";
			END IF;
			WHEN "11"=>--S3
			IF x='0' THEN
				q<='0';
				next_state<="11";
			ELSE
				q<='1';
				next_state<="00";
			END IF;
			WHEN others=>NULL;
		END CASE;
	END PROCESS;
	synchronous:PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			next_state<=current_state;
		END IF;
	END PROCESS;	
END behave;