example13-1.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY temprature IS
	PORT (
		clk: IN STD_LOGIC;
		thigh: IN STD_LOGIC;
		tlow: IN STD_LOGIC;
		hot: OUT STD_LOGIC;
		cool: OUT STD_LOGIC
		);
END temprature;

ARCHITECTURE behave_a OF temprature IS
	SUBTYPE state_type IS std_logic_vector(1 downto 0);
	SIGNAL current_state: state_type;
	SIGNAL next_state: state_type;
	CONSTANT be_hot: state_type:="11";
	CONSTANT be_cool: state_type:="10";
	CONSTANT just_right: state_type:="01";
BEGIN
	nxtstate:PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			current_state<=next_state;
		END IF;
	END PROCESS nxtstate;
	
	control:PROCESS(current_state)
	BEGIN
		CASE current_state IS
			WHEN just_right=>
			IF thigh='1' THEN
				next_state<=be_hot;
			ELSIF tlow='1' THEN
				next_state<=be_cool;
			ELSE
				next_state<=just_right;
			END IF;
			WHEN be_cool=>
			IF (tlow='0' and thigh='0') THEN
				next_state<=just_right;
			ELSIF thigh='1' THEN
				next_state<=be_hot;
			ELSE
				next_state<=be_cool;
			END IF;
			WHEN be_hot=>
			IF (tlow='0' and thigh='0') THEN
				next_state<=just_right;
			ELSIF tlow='1' THEN
				next_state<=be_cool;
			ELSE
				next_state<=be_hot;
			END IF;
			WHEN others=>NULL;
			next_state<=just_right;
		END CASE;
	END PROCESS control;
	
	output: PROCESS(current_state)
	BEGIN
		CASE current_state IS
			WHEN just_right=>
			hot<='0';
			cool<='0';
			WHEN be_hot=>
			hot<='1';
			cool<='0';
			WHEN be_cool=>
			hot<='0';
			cool<='1';
			WHEN others=>NULL;
			hot<='Z';
			cool<='Z';
		END CASE;
	END PROCESS output;
END behave_a;