example13-4.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY temprature IS
	PORT (
		clk: IN std_logic;
		thigh: IN std_logic;
		tlow: IN std_logic;
		hot: OUT std_logic;
		cool: OUT std_logic
		);
END temprature;
	
ARCHITECTURE behave_d OF temprature IS
	SUBTYPE state_type IS std_logic_vector(1 downto 0);
	SIGNAL state: state_type;
	CONSTANT be_hot: state_type:="11";
	CONSTANT be_cool: state_type:="10";
	CONSTANT just_right: state_type:="01";
BEGIN
	nxtstate_control:PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			CASE state IS
				WHEN just_right=>
				IF thigh='1' THEN
					state<=be_hot;
				ELSIF tlow='1' THEN
					state<=be_cool;
				ELSE
					state<=just_right;
				END IF;
				WHEN be_cool=>
				IF (tlow='0' and thigh='0') THEN
					state<=just_right;
				ELSIF thigh='1' THEN
					state<=be_hot;
				ELSE
					state<=be_cool;
				END IF;
				WHEN be_hot=>
				IF (tlow='0' and thigh='0') THEN
					state<=just_right;
				ELSIF tlow='1' THEN
					state<=be_cool;
				ELSE
					state<=be_hot;
				END IF;
				WHEN others=>NULL;
				state<=just_right;
			END CASE;
		END IF;
	END PROCESS nxtstate_control;
	
	output:PROCESS(state)
	BEGIN
		CASE state IS
			WHEN just_right=>
			hot<='0';
			cool<='0';
			WHEN be_hot=>
			hot<='1';
			cool<='0';
			WHEN be_cool=>
			hot<='0';
			cool<='1';
			WHEN others=>NULL;
			hot<='Z';
			cool<='Z';
		END CASE;
	END PROCESS output;
END behave_d;