example13-3.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY temprature IS
	PORT (
		clk: IN std_logic;
		thigh: IN std_logic;
		tlow: IN std_logic;
		hot: OUT std_logic;
		cool: OUT std_logic
		);
END temprature;

ARCHITECTURE behave_c OF temprature IS
	SUBTYPE state_type IS std_logic_vector(1 downto 0);
	SIGNAL state: state_type;
	CONSTANT be_hot: state_type:="11";--S3,too hot
	CONSTANT be_cool: state_type:="10";--S2,too cool
	CONSTANT just_right: state_type:="01";--S1,just right
BEGIN
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF thigh='1' THEN
				state<=be_hot;	
			ELSIF tlow='1' THEN
				state<=be_cool;	
			ELSE
				state<=just_right;
			END IF;
			-- output logic
			CASE state IS
				WHEN just_right=>
				hot<='0';
				cool<='0';
				WHEN be_cool=>
				hot<='0';
				cool<='1';
				WHEN be_hot=>
				hot<='1';
				cool<='0';
				WHEN others=>NULL;
				hot<='Z';
				cool<='Z';
			END CASE;
		END IF;
	END PROCESS;	  
END behave_c;