example13-5.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY temprature IS
	PORT (
		clk: IN STD_LOGIC;
		reset: IN std_logic;
		thigh: IN STD_LOGIC;
		tlow: IN STD_LOGIC;
		hot: OUT STD_LOGIC;
		cool: OUT STD_LOGIC
		);
END temprature;

ARCHITECTURE behave_d2 OF temprature IS
	SIGNAL state: std_logic_vector(1 downto 0);
BEGIN
	nxtstate_control:PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF reset='1' THEN
				state<="00";--just right
			ELSE
				state<=thigh & tlow;
			END IF;
		END IF;
	END PROCESS nxtstate_control;
	
	output:PROCESS(state)
	BEGIN
		hot<=state(1);
		cool<=state(0);
	END PROCESS output;
END behave_d2;