example8-9.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 70 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test1 IS
  GENERIC (int_rise, int_fall, ext_rise, ext_fall : TIME);
      PORT (in1 : IN Std_Logic;
            out1 : OUT Std_Logic);
END test1;
ARCHITECTURE example1 OF test1 IS
BEGIN
  p1 : PROCESS (in1)
    VARIABLE var1 : Std_Logic;
  BEGIN
    var1 := NOT (in1);
    IF var1 = '1' THEN
      out1 <= var1 AFTER (int_rise + ext_rise);
    ELSIF var1 = '0' THEN
      out1 <= var1 AFTER (int_fall + ext_fall);
    ELSE
      out1 <= var1 AFTER (int_fall + ext_fall);
    END IF;
  END PROCESS p1;
END example1;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test2 IS
  GENERIC (int_rise, int_fall, ext_rise, ext_fall : TIME);
  PORT (in1, in2, in3 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test2;
ARCHITECTURE example2 OF test2 IS
BEGIN
  p1 : PROCESS (in1, in2, in3)
    VARIABLE var1 : Std_Logic;
  BEGIN
    var1 := in1 AND in2 AND in3;
    IF var1 = '1' THEN
      out1 <= var1 AFTER (int_rise + ext_rise);
    ELSIF var1 = '0' THEN
      out1 <= var1 AFTER (int_fall + ext_fall);
    ELSE
      out1 <= var1 AFTER (int_fall + ext_fall);
    END IF;
  END PROCESS p1;
END example2;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY temp IS
  PORT (in1, in2, in3 : IN Std_Logic;
        out1, out2, out3, out4 : OUT Std_Logic);
END temp;
ARCHITECTURE arc OF temp IS
  COMPONENT test1
    PORT (in1 : IN Std_Logic;
          out1 : OUT Std_Logic);
  END COMPONENT;
  COMPONENT test2
    PORT (in1, in2, in3 : IN Std_Logic;
          out1 : OUT Std_Logic);
  END COMPONENT;
  SIGNAL s1, s2 : Std_Logic;
BEGIN
  U1 : test1 PORT MAP (in1, s1);
  U2 : test1 PORT MAP (in2, s2);
  U3 : test2 PORT MAP (s1, in3, s2, out1);
  U4 : test2 PORT MAP (in1, in3, s2, out2);
  U5 : test2 PORT MAP (s1, in3, in2, out3);
  U6 : test2 PORT MAP (in1, in3, in2, out4);
END arc;