example8-10.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY cpu IS
  PORT (clock : IN Std_Logic;
        addr : OUT Std_Logic_Vector (0 TO 3);
        data : INOUT Std_Logic_Vector (0 TO 3);
        interrupt : IN Std_Logic;
        reset : IN Std_Logic);
END cpu;
ARCHITECTURE arc OF cpu IS
  COMPONENT int_reg
    PORT (data : IN Std_Logic;
          regclock : IN Std_Logic;
          data_out : OUT Std_Logic);
  END COMPONENT;
  COMPONENT alu
    PORT (a, b : IN Std_Logic;
          c, carry : OUT Std_Logic);
  END COMPONENT;
  SIGNAL a, b, c, carry : Std_Logic_Vector (0 TO 3);
BEGIN
  reg_array : BLOCK
  BEGIN
    R1 : int_reg PORT MAP (data (0), clock, data (0));
    R2 : int_reg PORT MAP (data (1), clock, data (1));
    R3 : int_reg PORT MAP (data (2), clock, data (2));
    R4 : int_reg PORT MAP (data (3), clock, data (3));
  END BLOCK reg_array;

  shifter : BLOCK
  BEGIN
    A1 : alu PORT MAP (a (0), data (0), c (0), carry (0));
    A2 : alu PORT MAP (a (1), data (1), c (1), carry (1));
    A3 : alu PORT MAP (a (2), data (2), c (2), carry (2));
    A4 : alu PORT MAP (a (3), data (3), c (3), carry (3));

  shifter_reg : BLOCK
    BEGIN
      R1 : int_reg PORT MAP (b (0), clock, b (1));
  END BLOCK shifter_reg;
  END BLOCK shifter;
END arc;