example8-1.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 61 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT (in1, in2, in3 : IN Std_Logic;
        in4 : IN INTEGER;
        out1 : OUT INTEGER);
END test;

ARCHITECTURE example1 OF test IS
BEGIN
  PROCESS (in3)
    VARIABLE temp : INTEGER := 0;
  BEGIN
    IF in2 = '1' THEN
      temp := 0;
    ELSIF in1 = '1' THEN
      temp := in4;
    ELSE
      IF (in3'EVENT AND in3 ='1') AND (in3'LAST_VALUE = '0') THEN
        IF (temp = 255) THEN
          temp := 0;
        ELSE
          temp := temp + 1;
        END IF;
      END IF;
    END IF;
    out1 <= temp;
  END PROCESS;
END example1;

ARCHITECTURE example2 OF test IS
BEGIN
  PROCESS (in3)
    VARIABLE temp : INTEGER := 0;
  BEGIN
    IF in2 = '1' THEN
      temp := 0;
    ELSIF in1 = '1' THEN
      temp := in4;
    ELSE
      IF (in3'EVENT AND in3 ='1') AND (in3'LAST_VALUE = '0') THEN
        IF (temp = 65535) THEN
          temp := 0;
        ELSE
          temp := temp + 1;
        END IF;
      END IF;
    END IF;
    out1 <= temp;
  END PROCESS;
END example2;

CONFIGURATION con1 OF test IS
  FOR example1
  END FOR;
END con1;

CONFIGURATION con2 OF test IS
  FOR example2
  END FOR;
END con2;