example8-2.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test1 IS
  PORT (in1 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test1;
ARCHITECTURE example1 OF test1 IS
BEGIN
  out1 <= NOT (in1) AFTER 5 ns;
END example1;
CONFIGURATION con1 OF test1 IS
  FOR example1
  END FOR;
END con1;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test2 IS
  PORT (in1, in2, in3 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test2;
ARCHITECTURE example2 OF test2 IS
BEGIN
  out1 <= in1 AND in2 AND in3 AFTER 5 ns;
END example2;
CONFIGURATION con2 OF test2 IS
  FOR example2
  END FOR;
END con2;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY temp IS
  PORT (in1, in2, in3 : IN Std_Logic;
out1, out2, out3, out4 : OUT Std_Logic);
END temp;
ARCHITECTURE arc OF temp IS
  COMPONENT test1
  PORT (in1 : IN Std_Logic;
out1 : OUT Std_Logic);
      END COMPONENT;
  COMPONENT test2
  PORT (in1, in2, in3 : IN Std_Logic;
out1 : OUT Std_Logic);
END COMPONENT;
  SIGNAL s1, s2 : Std_Logic;
BEGIN
  U1 : test1 PORT MAP (in1, s1);
  U2 : test1 PORT MAP (in2, s2);
  U3 : test2 PORT MAP (s1, in3, s2, out1);
  U4 : test2 PORT MAP (in1, in3, s2, out2);
  U5 : test2 PORT MAP (s1, in3, in2, out3);
  U6 : test2 PORT MAP (in1, in3, in2, out4);
END arc;