example7-5.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 38 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test1 IS
  PORT (in1, in2 : IN Std_Logic;
            in3 : IN Std_Logic;
          out1 : BUFFER Std_Logic);
END test1;
ARCHITECTURE example1 OF test1 IS
BEGIN
  p1 : PROCESS (in2, in1)
  BEGIN
    IF in2 = '1' THEN
      out1 <= '0';
    ELSIF (in1'EVENT AND in1 = '1') THEN
      out1 <= in3;
    END IF;
  END PROCESS p1;
END example1;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test2 IS
  GENERIC (size : INTEGER := 2);
  PORT (in1, in2 : IN Std_Logic;
        in3 : IN Std_Logic_Vector (size - 1 DOWNTO 0);
        out1 : BUFFER Std_Logic_Vector (size - 1 DOWNTO 0));
END test2;
ARCHITECTURE example2 OF test2 IS
BEGIN
  p1 : PROCESS (in2, in1)
  BEGIN
    IF in2 = '1' THEN
      out1 <= (OTHERS => '0');
    ELSIF (in1'EVENT AND in1 = '1') THEN
      out1 <= in3;
    END IF;
  END PROCESS p1;
END example2;