example7-12.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY temp IS
  PORT (in1, in2, in3 : IN Std_Logic;
          out1 : OUT Std_Logic);
END temp;
ARCHITECTURE example OF temp IS
  COMPONENT and2
    PORT (a, b : IN Std_Logic;
          c : OUT Std_Logic);
END COMPONENT;
COMPONENT or2
  PORT (a, b : IN Std_Logic;
        c : OUT Std_Logic);
END COMPONENT;
COMPONENT inv
  PORT (a : IN Std_Logic;
        c : OUT Std_Logic);
  END COMPONENT;
  SIGNAL s1, s2, s3 : Std_Logic;
BEGIN
  U1 : inv PORT MAP (in3, s3);
  U2 : and2 PORT MAP (s3, in2, s2);
  U3 : and2 PORT MAP (in1, in2, s1);
  U4 : or2 PORT MAP (s1, s2, out1);
END example;