example7-9.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 41 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY temp1 IS
  PORT (in1, in2 : IN Std_Logic;
            in3 : IN Std_Logic;
           out1 : BUFFER Std_Logic);
END temp1;
ARCHITECTURE arc1 OF temp1 IS
  SIGNAL s : Std_Logic;
BEGIN
  p1 : PROCESS (in2, in1)
  BEGIN
    IF in2 = '1' THEN
      out1 <= '0';
    ELSIF (in1'EVENT AND in1 = '1') THEN
      s <= in3;
      out1 <= s;
    END IF;
  END PROCESS p1;
END arc1;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY temp2 IS
  PORT (in1, in2 : IN Std_Logic;
            in3 : IN Std_Logic;
           out1 : BUFFER Std_Logic);
END temp2;
ARCHITECTURE arc2 OF temp2 IS
  SIGNAL s : Std_Logic;
BEGIN
  p1 : PROCESS (in2, in1)
  BEGIN
    IF in2 = '1' THEN
      out1 <= '1';
    ELSIF (in1'EVENT AND in1 = '1') THEN
      s <= in3;
      out1 <= s;
    END IF;
  END PROCESS p1;
END arc2;