example7-6.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 42 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test3 IS
  PORT (in1, in2, in3 : IN Std_Logic;
        in4 : IN Std_Logic;
        out1 : BUFFER Std_Logic);
END test3;
ARCHITECTURE example3 OF test3 IS
BEGIN
  p1 : PROCESS (in2, in1)
  BEGIN
    IF in2 = '1' THEN
      out1 <= '0';
    ELSIF (in1'EVENT AND in1 = '1') THEN
      IF in3 = '1' THEN
        out1 <= in4;
      END IF;
    END IF;
  END PROCESS p1;
END example3;

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test4 IS
  GENERIC (size : INTEGER := 2);
  PORT (in1, in2, in3 : IN Std_Logic;
        in4 : IN Std_Logic_Vector (size - 1 DOWNTO 0);
        out1 : BUFFER Std_Logic_Vector (size - 1 DOWNTO 0));
END test4;
ARCHITECTURE example4 OF test4 IS
BEGIN
  p1 : PROCESS (in2, in1)
  BEGIN
    IF in2 = '1' THEN
      out1 <= (OTHERS => '0');
    ELSIF (in1'EVENT AND in1 = '1') THEN
      IF in3 = '1' THEN
        out1 <= in4;
      END IF;
    END IF;
  END PROCESS p1;
END example4;