example7-7.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test5 IS
  GENERIC (size : INTEGER := 2);
  PORT (in1, in2 : IN Std_Logic;
        in3, in4 : IN Std_Logic;
           in5 : IN Std_Logic_Vector (size - 1 DOWNTO 0);
          out1 : BUFFER Std_Logic_Vector (size - 1 DOWNTO 0));
END test5;
ARCHITECTURE example5 OF test5 IS
BEGIN
  p1 : PROCESS (in1)
  BEGIN
    IF in3 = '1' THEN
      out1 <= (OTHERS => '0');
    ELSIF in4 = '1' THEN
      out1 <= (OTHERS => '1');
    ELSIF (in1'EVENT AND in1 = '1') THEN
      IF in2 = '1' THEN
        out1 <= in5;
      ELSE
        out1 <= out1;
      END IF;
    END IF;
  END PROCESS p1;
END example5;