example7-1.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE example IS
  CONSTANT con1 : REAL := 3.1415926;
  CONSTANT con2 : INTEGER;
  FUNCTION fun1 (a, b, c : REAL) RETURN REAL;
  COMPONENT com1 IS
    GENERIC (t1, t2 : TIME := 3 ns);
    PORT (in1, in2 : Std_Logic);
  END COMPONENT com1;
END PACKAGE example;
PACKAGE BODY example IS
  CONSTANT con2 : INTEGER := 5;
  FUNCTION fun1 (a, b, c : REAL) RETURN REAL IS
  BEGIN
    RETURN (a + b + c)/3.0;
  END FUNCTION fun1;
END PACKAGE BODY example;