example16-8.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY counter16 IS
	PORT (
		clk: IN std_logic;
		reseta: IN std_logic;
		resetb: IN std_logic;
		load: IN std_logic;
		enablea: IN std_logic;
		enableb: IN std_logic;
		byone: IN std_logic;
		counta: BUFFER std_logic_vector (15 downto 0);
		countb: BUFFER std_logic_vector (15 downto 0)
		);
END counter16;

ARCHITECTURE behave OF counter16 IS
BEGIN
	countera:PROCESS(clk,reseta)
	BEGIN
		IF reseta='1' THEN
			counta<=(others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			IF load='1' THEN
				counta<=countb;
			ELSIF enablea='1' THEN
				IF byone='1' THEN
					counta<=counta+1;
				ELSE
					counta<=counta+2;
				END IF;
			ELSE
				counta<=counta;
			END IF;
		END IF;
	END PROCESS countera;
	
	counterb:PROCESS(clk,resetb) 
		BEGIN
		IF resetb='1' THEN
			countb<=(others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			IF load='1' THEN
				countb<=counta;
			ELSIF enableb='1' THEN
				IF byone='1' THEN
					countb<=countb+1;
				ELSE
					countb<=countb+2;
				END IF;
			ELSE
				countb<=countb;
			END IF;
		END IF;
	END PROCESS counterb; 
END behave;