example16-3.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY counter8 IS
	PORT (
		clk: IN std_logic;
		reseta: IN std_logic;
		resetb: IN std_logic;
		resetc: IN std_logic;
		countera: BUFFER std_logic_vector (7 downto 0);
		counterb: BUFFER std_logic_vector (7 downto 0);
		counterc: BUFFER std_logic_vector (7 downto 0)
		);
END counter8;

ARCHITECTURE behave OF counter8 IS
BEGIN
	ca:PROCESS(clk,reseta)
	BEGIN
		IF reseta='1' THEN
			countera<=(others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			countera<=countera+1;
		END IF;
	END PROCESS ca;
	
	cb:PROCESS(clk,resetb)
	BEGIN
		IF resetb='1' THEN
			counterb<=(others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			counterb<=counterb+1;
		END IF;
	END PROCESS cb;  
	
	cc:PROCESS(clk,resetc)
	BEGIN
		IF resetc='1' THEN
			counterc<=(others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			counterc<=counterc+1;
		END IF;
	END PROCESS cc;
END behave;