example16-10.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY unreal IS
	PORT (
		a: IN std_logic;
		b: IN std_logic;
		c: IN std_logic;
		d: IN std_logic;
		y: BUFFER std_logic
		);
END unreal;

ARCHITECTURE behave OF unreal IS
	SIGNAL x: std_logic;
	ATTRIBUTE synthesis_off OF x:SIGNAL IS true;	--retain node description
BEGIN
	x<=a or b or c;
	y<=x or d;
END behave;