example16-13.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
	
ENTITY pterm IS
		PORT (
			a: IN std_logic;
		b: IN std_logic;
			c: IN std_logic;
			d: IN std_logic;
		e: IN std_logic;
			f: IN std_logic;
			g: IN std_logic;
		h: IN std_logic;
			i: IN std_logic;
			j: IN std_logic;
		k: IN std_logic;
			l: IN std_logic;
			x: OUT std_logic
		);
END pterm;
	
ARCHITECTURE behave OF pterm IS
		SIGNAL x1: std_logic;
	SIGNAL x2: std_logic;
		SIGNAL x3: std_logic;
	ATTRIBUTE synthesis_off OF x1,x2,x3: SIGNAL IS true;
BEGIN
		x1<=(a and b) xor (c or d);
	x2<=(e and f) xor (g or h);
		x3<=(i and j) xor (k and l);
	x<=x1 xor x2 xor x3;  
END behave;