example16-7.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 36 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY counter_complex IS
	PORT (
		clk: IN std_logic;
		reseta: IN std_logic;
		resetb: IN std_logic;
		countera: BUFFER std_logic_vector (7 downto 0);
		counterb: BUFFER std_logic_vector (7 downto 0)		
		);
END counter_complex;

ARCHITECTURE behave OF counter_complex IS
BEGIN
	ca:PROCESS(clk,reseta,resetb)
	BEGIN
		IF reseta='1' xor resetb='1' THEN	--complex asynchronous reset
			countera<=(0=>'1',others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			countera<=countera+1;
		END IF;
	END PROCESS ca;
	
	cb:PROCESS(clk,reseta,resetb)
	BEGIN
		IF reseta='1' xor resetb='1' THEN	--complex asynchronous reset
			counterb<=(1=>'1',others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			counterb<=counterb+1;
		END IF;
	END PROCESS cb;  
END behave;