example16-4.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 51 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY counter IS
	PORT (
		clk: IN std_logic;
		reseta: IN std_logic;
		resetb: IN std_logic;
		resetc: IN std_logic;
		countera: BUFFER std_logic_vector (7 downto 0);
		counterb: BUFFER std_logic_vector (7 downto 0);
		counterc: BUFFER std_logic_vector (7 downto 0)
		);
END counter;

ARCHITECTURE behave OF counter IS
BEGIN
	ca:PROCESS(clk,reseta)
	BEGIN
		IF reseta='1' THEN	--asynchronous reset
			countera<=(others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			countera<=countera+1;
		END IF;
	END PROCESS ca;
	
	cb:PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF resetb='1' THEN --synchronous reset
				counterb<=(others=>'0');
			ELSE
				counterb<=counterb+1;
			END IF;
		END IF;
	END PROCESS cb;  
	
	cc:PROCESS(clk,resetc)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF resetc='1' THEN	--synchronous reset
				counterc<=(others=>'0');
			ELSE
				counterc<=counterc+1;
			END IF;	
		END IF;
	END PROCESS cc;
END behave;