example16-11.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 40 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY counter28 is
	PORT (
		clk: IN std_logic;
		reset: IN std_logic;
		outenable: IN std_logic;
		shift: IN std_logic;
		count: BUFFER std_logic_vector (27 downto 0)
		);
END counter28;

ARCHITECTURE behave OF counter28 IS
	SIGNAL enable_high: std_logic;
	ATTRIBUTE synthesis_off OF enable_high:SIGNAL IS true;
	SIGNAL cnt: std_logic_vector(27 downto 0);
	ALIAS lowcnt: std_logic_vector(14 downto 0) is cnt(14 downto 0);
	ALIAS highcnt: std_logic_vector(12 downto 0) is cnt(27 downto 15);
BEGIN
	PROCESS(clk,reset)
	BEGIN
		IF reset='1' THEN
			cnt<=(others=>'0');
		ELSIF clk'EVENT and clk='1' THEN
			IF shift='1' THEN
				cnt<=count(26 downto 0) & count(27);
			ELSE
				lowcnt<=lowcnt+1;
				IF enable_high='1' THEN
					highcnt<=highcnt+1;
				END IF;
			END IF;
		END IF;
	END PROCESS;
	enable_high<='1' WHEN lowcnt="111111111111111" ELSE '0';
	count<=cnt WHEN outenable='1' else (others=>'Z');	
END behave;