example12-18.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY reg IS
	PORT (
		data: IN STD_LOGIC_VECTOR (7 downto 0);
		clk: IN STD_LOGIC;
		enable: IN STD_LOGIC;
		q: OUT STD_LOGIC_VECTOR (7 downto 0)
		);
END reg;

ARCHITECTURE behave OF reg IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF enable='1' THEN
				q<=data;
			END IF;
		END IF;
	END PROCESS;
END behave;