example12-8.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY dff_async_set_reset IS
	PORT (
		clk: IN STD_LOGIC;
		set: IN STD_LOGIC;
		reset: IN STD_LOGIC;
		data: IN STD_LOGIC;
		q: OUT STD_LOGIC
		);
END dff_async_set_reset;

ARCHITECTURE behave OF dff_async_set_reset IS
BEGIN
	PROCESS(clk,set,reset)
	BEGIN
		IF (reset='1') THEN
			q<='0';
		ELSIF (set = '1') THEN
			q <= '1';
		ELSIF (clk'EVENT and clk = '1') THEN
			q <= data;
		END IF;
	END PROCESS;
END behave;