example12-10.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY dff_sync_reset IS
	PORT (
		clk: IN STD_LOGIC;
		data: IN STD_LOGIC;
		reset: IN STD_LOGIC;
		q: OUT STD_LOGIC
		);
END dff_sync_reset;

ARCHITECTURE behave OF dff_sync_reset IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF (clk'EVENT and clk = '1') THEN
			IF (reset = '1') THEN
				q <= '0';
			ELSE
				q <= data;
			END IF;
		END IF;
	END PROCESS;	
END behave;