example12-13.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY Toggle_async_set IS
	PORT (
		clk: IN STD_LOGIC;
		set: IN STD_LOGIC;
		q: OUT STD_LOGIC
		);
END Toggle_async_set;

ARCHITECTURE behave OF Toggle_async_set IS
	SIGNAL temp_q:std_logic;
BEGIN
	PROCESS(clk,set)
	BEGIN
		IF set='1' THEN
			temp_q<='1';
		ELSIF clk'EVENT and clk='1' THEN
			temp_q<= not temp_q;
		END IF;
		q<=temp_q;
	END PROCESS;
END behave;