example12-21.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;

ENTITY counter8_sync IS
	PORT (
		clk: IN STD_LOGIC;
		countin: IN integer range 0 to 255;
		set: IN STD_LOGIC;
		reset: IN STD_LOGIC;
		countq: OUT integer range 0 to 255
		);
END counter8_sync;

ARCHITECTURE behave OF counter8_sync IS
	SIGNAL countq_temp: integer range 0 to 255;
BEGIN
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF reset='1' THEN
				countq_temp<=0;
			ELSIF set='1' THEN
				countq_temp<=countin;
			ELSE
				countq_temp<=countq_temp+1;
			END IF;
		END IF;
	END PROCESS;
	countq<=countq_temp;
END behave;