example12-15.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY jk IS
	PORT (
		j: IN STD_LOGIC;
		k: IN STD_LOGIC;
		clk: IN STD_LOGIC;
		q: OUT STD_LOGIC
		);
END jk;

ARCHITECTURE behave OF jk IS
	SIGNAL q_temp : std_logic;
BEGIN
	PROCESS(clk)
		VARIABLE jk_temp : std_logic_vector(1 downto 0);
	BEGIN
		IF clk'EVENT and clk='1' THEN
			jk_temp:=(j & k);
			CASE jk_temp IS
				WHEN "01" =>
				q_temp<='1';
				WHEN "10" =>
				q_temp<='0';
				WHEN "00" =>
				q_temp<=q_temp;
				WHEN others =>
				q_temp<='X';
			END CASE;
		END IF;
	END PROCESS;
	q<=q_temp;
END behave;