example12-1.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY  latch1 IS
PORT(data: IN std_logic;
	s: IN std_logic;
	reset: IN std_logic;
	q: OUT std_logic);
END latch1;

ARCHITECTURE behave OF latch1 IS
BEGIN
	PROCESS(data,s,reset)
	BEGIN
		IF reset='1' THEN
			q<='0';
		ELSIF s='1' THEN
			q<=data;
		END IF;
	END PROCESS;
END behave;