example12-4.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 28 行

LIBRARY  IEEE;
USE IEEE.std_logic_1164.all;

ENTITY  latch4 IS
	PORT (
		clk: IN STD_LOGIC;
		reset: IN STD_LOGIC;
		data: IN STD_LOGIC;
		load: IN std_logic;
		q: OUT STD_LOGIC
		);
END latch4;

ARCHITECTURE behave OF latch4 IS
BEGIN
	PROCESS(clk,reset)
	BEGIN
		IF reset='1' THEN
			q<='0';
		ELSIF clk'EVENT and clk='1' THEN
			IF load='1' THEN
				q<=data;
			END IF;
		END IF;
	END PROCESS;
	
END behave;