example12-20.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY reg_round IS
	PORT (
		data: IN STD_LOGIC_vector (7 downto 0);
		clk: IN STD_LOGIC;
		control: IN STD_LOGIC_vector(2 downto 0);
		q: OUT STD_LOGIC_vector (7 downto 0)
		);
END reg_round;

ARCHITECTURE behave OF reg_round IS
	SIGNAL q_temp: std_logic_vector(7 downto 0);
BEGIN
	PROCESS(clk)
		VARIABLE ctl: std_logic_vector(2 downto 0);
	BEGIN
		ctl:=control;
		IF clk'EVENT and clk='1' THEN
			CASE ctl IS
				WHEN "000"=>
				q_temp<=data;
				WHEN "001"=>
				q_temp<=data(6 downto 0) & data(7);
				WHEN "010"=>
				q_temp<=data(5 downto 0) & data(7 downto 6);
				WHEN "011"=>
				q_temp<=data(4 downto 0) & data(7 downto 5);
				WHEN "100"=>
				q_temp<=data(3 downto 0) & data(7 downto 4);
				WHEN "101"=>
				q_temp<=data(2 downto 0) & data(7 downto 3);
				WHEN "110"=>
				q_temp<=data(1 downto 0) & data(7 downto 2);
				WHEN "111"=>
				q_temp<=data(0) & data(7 downto 1);
				WHEN others=>
				q_temp<="XXXXXXXX";
			END CASE;				
		END IF;
	END PROCESS;
	q<=q_temp;
END behave;