example12-9.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY dff_sync_set IS
	PORT (
		clk: IN STD_LOGIC;
		data: IN STD_LOGIC;
		set: IN STD_LOGIC;
		q: OUT STD_LOGIC
		);
END dff_sync_set;

ARCHITECTURE behave OF dff_sync_set IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF (clk'EVENT and clk = '1') THEN
			IF (set = '1') THEN
				q <= '1';
			ELSE
				q <= data;
			END IF;
		END IF;
	END PROCESS;	
END behave;