example12-17.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 41 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY jk_async_set_reset IS
	PORT (
		j: IN STD_LOGIC;
		k: IN STD_LOGIC;
		clk: IN STD_LOGIC;
		set: IN std_logic;
		reset: IN std_logic;
		q: OUT STD_LOGIC
		);
END jk_async_set_reset;

ARCHITECTURE behave OF jk_async_set_reset IS
	SIGNAL q_temp : std_logic;
BEGIN
	PROCESS(clk,set,reset)
				VARIABLE jk_temp : std_logic_vector(1 downto 0);
	BEGIN
		IF reset='1' THEN
			q_temp<='0';
		ELSIF set='1' THEN
			q_temp<='1';
		ELSIF clk'EVENT and clk='1' THEN
			IF j='0' and k='1' THEN
				q_temp<='1';
			ELSIF j='1' and k='0' THEN
				q_temp<='0';
			ELSIF j='1' and k='1' THEN
				q_temp<=not q_temp;
			ELSIF j='0' and k='0' THEN
				q_temp<=q_temp;
			ELSE
				q_temp<='X';
			END IF;			
		END IF;
	END PROCESS;
	q<=q_temp;
END behave;