example12-2.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY latch2 IS
	PORT (
		data1: IN std_logic;
		data2: IN std_logic;
		data3: IN std_logic;
		s1: IN std_logic;
		s2: IN std_logic;
		s3: IN std_logic;
		reset: IN std_logic;
		q: OUT std_logic
		);
END latch2;

ARCHITECTURE behave OF latch2 IS
BEGIN
	PROCESS(data1,data2,data3,s1,s2,s3,reset)
	BEGIN
		IF reset='1' THEN
			q<='0';
		ELSIF s1='1'THEN
			q<=data1;
		ELSIF s2='1' THEN
			q<=data2;
		ELSIF s3='1' THEN
			q<=data3;
		END IF;
	END PROCESS;
END behave;