📄 arbit1.sum
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Cell: arbit1 View: INTERFACE Library: work
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Total accumulated area :
Number of BUFG : 1
Number of CLB Flip Flops : 53
Number of CY4 : 7
Number of FG Function Generators : 138
Number of H Function Generators : 32
Number of IBUF : 92
Number of IOB Output Flip Flops : 40
Number of OBUF : 29
Number of OBUFT : 24
Number of Packed CLBs : 67
Number of ports : 171
Number of nets : 550
Number of instances : 428
Number of references to this view : 0
Cell Library References Total Area
BUFG xi4xl 1 x 1 1 BUFG
CY4 xi4xl 7 x 1 7 CY4
CY4_17 xi4xl 1 x 1 1 CY4_17
CY4_18 xi4xl 5 x 1 5 CY4_18
CY4_21 xi4xl 1 x 1 1 CY4_21
F2_LUT xi4xl 9 x 1 9 FG Function Generators
F3_LUT xi4xl 12 x 1 12 FG Function Generators
F4_LUT xi4xl 117 x 1 117 FG Function Generators
FDCE xi4xl 53 x 1 53 CLB Flip Flops
GND xi4xl 1 x 1 1 GND
H2_LUT xi4xl 10 x 1 10 H Function Generators
H3_LUT xi4xl 22 x 1 22 H Function Generators
IBUF xi4xl 92 x 1 92 IBUF
INV xi4xl 3 x 1 3 INV
OBUF xi4xl 29 x 1 29 OBUF
OBUFT xi4xl 24 x 1 24 OBUFT
OFDX xi4xl 40 x 1 40 IOB Output Flip Flops
VCC xi4xl 1 x 1 1 VCC
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Device Utilization for 4010xlPQ100
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Resource Used Avail Utilization
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IOs 171 77 222.08%
FG Function Generators 138 800 17.25%
H Function Generators 32 400 8.00%
CLB Flip Flops 53 800 6.63%
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This design does not fit in the device specified!
Trying an alternate device ...
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Device Utilization for 4013XLCB228
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Resource Used Avail Utilization
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IOs 171 192 89.06%
FG Function Generators 138 1152 11.98%
H Function Generators 32 576 5.56%
CLB Flip Flops 53 1152 4.60%
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Using wire table: 4013xl-3_avg
Clock Frequency Report
Clock : Frequency
------------------------------------
clk : 23.9 MHz
Slack Table at End Points
End points Slack Arrival Required
rise fall rise fall
reg_ram_addr(9)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(5)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(6)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(12)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(2)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(11)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(10)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(1)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(4)/D : n/a 41.55 41.55 n/a n/a
reg_ram_addr(3)/D : n/a 41.55 41.55 n/a n/a
Critical Path Report
Critical path #1, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(1)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2742/O F4_LUT 8.83 32.41 up 2.77
nx2708/O F4_LUT 4.57 36.98 up 2.77
nx511/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(12)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
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unconstrained path
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Critical path #2, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(2)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2742/O F4_LUT 8.83 32.41 up 2.77
nx2708/O F4_LUT 4.57 36.98 up 2.77
nx511/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(12)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
Critical path #3, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(0)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2748/O F4_LUT 8.83 32.41 up 2.77
nx2714/O F4_LUT 4.57 36.98 up 2.77
nx517/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(6)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
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data required time not specified
data arrival time 41.55
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unconstrained path
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Critical path #4, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
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