arbit1.sum
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SUM
392 行
reg_ram_state(1)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2748/O F4_LUT 8.83 32.41 up 2.77
nx2714/O F4_LUT 4.57 36.98 up 2.77
nx517/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(6)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
Critical path #5, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(2)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2748/O F4_LUT 8.83 32.41 up 2.77
nx2714/O F4_LUT 4.57 36.98 up 2.77
nx517/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(6)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
Critical path #6, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(0)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2749/O F4_LUT 8.83 32.41 up 2.77
nx2715/O F4_LUT 4.57 36.98 up 2.77
nx518/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(5)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
Critical path #7, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(1)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2749/O F4_LUT 8.83 32.41 up 2.77
nx2715/O F4_LUT 4.57 36.98 up 2.77
nx518/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(5)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
Critical path #8, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(2)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2749/O F4_LUT 8.83 32.41 up 2.77
nx2715/O F4_LUT 4.57 36.98 up 2.77
nx518/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(5)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
Critical path #9, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(0)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2745/O F4_LUT 8.83 32.41 up 2.77
nx2711/O F4_LUT 4.57 36.98 up 2.77
nx514/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(9)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
Critical path #10, (unconstrained path)
NAME GATE ARRIVAL LOAD
--------------------------------------------------------------------------------------------
clock information not specified
delay thru clock network 0.00 (ideal)
reg_ram_state(1)/Q FDCE 0.00 1.70 up 7.03
nx2729/O F3_LUT 8.83 10.53 up 6.08
nx2768/O H3_LUT 7.28 17.81 up 2.77
nx2671/O F4_LUT 4.57 22.38 up 2.77
nx2723/O H3_LUT 1.20 23.58 up 7.03
nx2745/O F4_LUT 8.83 32.41 up 2.77
nx2711/O F4_LUT 4.57 36.98 up 2.77
nx514/O F4_LUT 4.57 41.55 up 2.77
reg_ram_addr(9)/D FDCE 0.00 41.55 up 0.00
data arrival time 41.55
data required time (default specified - setup time) not specified
--------------------------------------------------------------------------------------------
data required time not specified
data arrival time 41.55
----------
unconstrained path
--------------------------------------------------------------------------------------------
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