cnt_24.map.qmsg

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Web Edition " "Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 05 15:07:06 2005 " "Info: Processing started: Sun Jun 05 15:07:06 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cnt_24 -c cnt_24 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt_24 -c cnt_24" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt_24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt_24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt_24-one " "Info: Found design unit 1: cnt_24-one" {  } { { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt_24 " "Info: Found entity 1: cnt_24" {  } { { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "clock.vhd 2 1 " "Info: Using design file clock.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-behv " "Info: Found design unit 1: clock-behv" {  } { { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 22 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cy1 clock.vhd(23) " "Info: (10035) Verilog HDL or VHDL information at clock.vhd(23): object \"cy1\" declared but not used" {  } { { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 23 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cy2 clock.vhd(23) " "Info: (10035) Verilog HDL or VHDL information at clock.vhd(23): object \"cy2\" declared but not used" {  } { { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 23 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cnt60a.vhd 2 1 " "Info: Using design file cnt60a.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt60a-one " "Info: Found design unit 1: cnt60a-one" {  } { { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt60a " "Info: Found entity 1: cnt60a" {  } { { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt60a cnt60a:u1 " "Info: Elaborating entity \"cnt60a\" for hierarchy \"cnt60a:u1\"" {  } { { "clock.vhd" "u1" { Text "E:/liuwei/VHDL/clk/clock.vhd" 39 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_24 cnt_24:u3 " "Info: Elaborating entity \"cnt_24\" for hierarchy \"cnt_24:u3\"" {  } { { "clock.vhd" "u3" { Text "E:/liuwei/VHDL/clk/clock.vhd" 41 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cq cnt_24.vhd(20) " "Info: (10035) Verilog HDL or VHDL information at cnt_24.vhd(20): object \"cq\" declared but not used" {  } { { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 20 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_24:u3\|templ\[0\]~51 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt_24:u3\|templ\[0\]~51\"" {  } { { "cnt_24.vhd" "templ\[0\]~51" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 18 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt60a:u2\|\\p1:templ\[0\] cnt60a:u1\|\\p1:templ\[0\] " "Info: Duplicate register \"cnt60a:u2\|\\p1:templ\[0\]\" merged to single register \"cnt60a:u1\|\\p1:templ\[0\]\"" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "184 " "Info: Implemented 184 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "151 " "Info: Implemented 151 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 05 15:07:11 2005 " "Info: Processing ended: Sun Jun 05 15:07:11 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}