clock.tan.qmsg

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!

{ "Info" "ITDB_FULL_TCO_RESULT" "clk q3h\[1\] q3h\[1\]~reg0 11.700 ns register " "Info: tco from clock \"clk\" to destination pin \"q3h\[1\]\" through register \"q3h\[1\]~reg0\" is 11.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 91 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 91; CLK Node = 'clk'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns q3h\[1\]~reg0 2 REG LC1_A17 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_A17; Fanout = 1; REG Node = 'q3h\[1\]~reg0'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.400 ns" { clk q3h[1]~reg0 } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk q3h[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out q3h[1]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.800 ns + Longest register pin " "Info: + Longest register to pin delay is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q3h\[1\]~reg0 1 REG LC1_A17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A17; Fanout = 1; REG Node = 'q3h\[1\]~reg0'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { q3h[1]~reg0 } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(6.300 ns) 8.800 ns q3h\[1\] 2 PIN PIN_82 0 " "Info: 2: + IC(2.500 ns) + CELL(6.300 ns) = 8.800 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'q3h\[1\]'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "8.800 ns" { q3h[1]~reg0 q3h[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 71.59 % " "Info: Total cell delay = 6.300 ns ( 71.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 28.41 % " "Info: Total interconnect delay = 2.500 ns ( 28.41 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "8.800 ns" { q3h[1]~reg0 q3h[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.800 ns" { q3h[1]~reg0 q3h[1] } { 0.000ns 2.500ns } { 0.000ns 6.300ns } } }  } 0}  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk q3h[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out q3h[1]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "8.800 ns" { q3h[1]~reg0 q3h[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.800 ns" { q3h[1]~reg0 q3h[1] } { 0.000ns 2.500ns } { 0.000ns 6.300ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "cnt60:u1\|qh\[0\] ts_set clk -5.800 ns register " "Info: th for register \"cnt60:u1\|qh\[0\]\" (data pin = \"ts_set\", clock pin = \"clk\") is -5.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 91 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 91; CLK Node = 'clk'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cnt60:u1\|qh\[0\] 2 REG LC3_C35 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_C35; Fanout = 5; REG Node = 'cnt60:u1\|qh\[0\]'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.400 ns" { clk cnt60:u1|qh[0] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt60:u1|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt60:u1|qh[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "cnt60.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns ts_set 1 PIN PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'ts_set'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { ts_set } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.400 ns) 7.500 ns cnt60:u1\|qh~164 2 COMB LC1_C32 4 " "Info: 2: + IC(1.200 ns) + CELL(1.400 ns) = 7.500 ns; Loc. = LC1_C32; Fanout = 4; COMB Node = 'cnt60:u1\|qh~164'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.600 ns" { ts_set cnt60:u1|qh~164 } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.000 ns) 9.500 ns cnt60:u1\|qh\[0\] 3 REG LC3_C35 5 " "Info: 3: + IC(1.000 ns) + CELL(1.000 ns) = 9.500 ns; Loc. = LC3_C35; Fanout = 5; REG Node = 'cnt60:u1\|qh\[0\]'" {  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.000 ns" { cnt60:u1|qh~164 cnt60:u1|qh[0] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns 76.84 % " "Info: Total cell delay = 7.300 ns ( 76.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 23.16 % " "Info: Total interconnect delay = 2.200 ns ( 23.16 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "9.500 ns" { ts_set cnt60:u1|qh~164 cnt60:u1|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { ts_set ts_set~out cnt60:u1|qh~164 cnt60:u1|qh[0] } { 0.000ns 0.000ns 1.200ns 1.000ns } { 0.000ns 4.900ns 1.400ns 1.000ns } } }  } 0}  } { { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt60:u1|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt60:u1|qh[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/clock.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "9.500 ns" { ts_set cnt60:u1|qh~164 cnt60:u1|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { ts_set ts_set~