cnt_24.tan.qmsg

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!

{ "Info" "ITDB_FULL_TCO_RESULT" "clk q3h\[3\] cnt_24:u3\|temph\[3\] 11.300 ns register " "Info: tco from clock \"clk\" to destination pin \"q3h\[3\]\" through register \"cnt_24:u3\|temph\[3\]\" is 11.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 74 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cnt_24:u3\|temph\[3\] 2 REG LC2_F25 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_F25; Fanout = 3; REG Node = 'cnt_24:u3\|temph\[3\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.400 ns" { clk cnt_24:u3|temph[3] } "NODE_NAME" } "" } } { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temph[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temph[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns + Longest register pin " "Info: + Longest register to pin delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_24:u3\|temph\[3\] 1 REG LC2_F25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_F25; Fanout = 3; REG Node = 'cnt_24:u3\|temph\[3\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { cnt_24:u3|temph[3] } "NODE_NAME" } "" } } { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(6.300 ns) 8.400 ns q3h\[3\] 2 PIN PIN_20 0 " "Info: 2: + IC(2.100 ns) + CELL(6.300 ns) = 8.400 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'q3h\[3\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "8.400 ns" { cnt_24:u3|temph[3] q3h[3] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 75.00 % " "Info: Total cell delay = 6.300 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 25.00 % " "Info: Total interconnect delay = 2.100 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "8.400 ns" { cnt_24:u3|temph[3] q3h[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { cnt_24:u3|temph[3] q3h[3] } { 0.000ns 2.100ns } { 0.000ns 6.300ns } } }  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temph[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temph[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "8.400 ns" { cnt_24:u3|temph[3] q3h[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { cnt_24:u3|temph[3] q3h[3] } { 0.000ns 2.100ns } { 0.000ns 6.300ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "cnt60a:u2\|ql\[0\] m_set clk -1.100 ns register " "Info: th for register \"cnt60a:u2\|ql\[0\]\" (data pin = \"m_set\", clock pin = \"clk\") is -1.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 74 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cnt60a:u2\|ql\[0\] 2 REG LC3_F8 6 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_F8; Fanout = 6; REG Node = 'cnt60a:u2\|ql\[0\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.400 ns" { clk cnt60a:u2|ql[0] } "NODE_NAME" } "" } } { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt60a:u2|ql[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt60a:u2|ql[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns m_set 1 PIN PIN_56 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 2; PIN Node = 'm_set'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { m_set } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 3.500 ns cnt60a:u2\|ql~258 2 COMB LC4_F8 3 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC4_F8; Fanout = 3; COMB Node = 'cnt60a:u2\|ql~258'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "1.500 ns" { m_set cnt60a:u2|ql~258 } "NODE_NAME" } "" } } { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 4.800 ns cnt60a:u2\|ql\[0\] 3 REG LC3_F8 6 " "Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 4.800 ns; Loc. = LC3_F8; Fanout = 6; REG Node = 'cnt60a:u2\|ql\[0\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "1.300 ns" { cnt60a:u2|ql~258 cnt60a:u2|ql[0] } "NODE_NAME" } "" } } { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.400 ns 91.67 % " "Info: Total cell delay = 4.400 ns ( 91.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 8.33 % " "Info: Total interconnect delay = 0.400 ns ( 8.33 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "4.800 ns" { m_set cnt60a:u2|ql~258 cnt60a:u2|ql[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.800 ns" { m_set m_set~out cnt60a:u2|ql~258 cnt60a:u2|ql[0] } { 0.000ns 0.000ns 0.100ns 0.300ns } { 0.000ns 2.000ns 1.400ns 1.000ns } } }  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt60a:u2|ql[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter