📄 cnt_24.tan.qmsg

📁 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt_24:u3\|temp\[1\] register cnt_24:u3\|temp\[31\] 75.19 MHz 13.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 75.19 MHz between source register \"cnt_24:u3\|temp\[1\]\" and destination register \"cnt_24:u3\|temp\[31\]\" (period= 13.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.200 ns + Longest register register " "Info: + Longest register to register delay is 12.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_24:u3\|temp\[1\] 1 REG LC8_F30 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_F30; Fanout = 3; REG Node = 'cnt_24:u3\|temp\[1\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { cnt_24:u3|temp[1] } "NODE_NAME" } "" } } { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.700 ns) 1.700 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC2_F29 2 " "Info: 2: + IC(1.000 ns) + CELL(0.700 ns) = 1.700 ns; Loc. = LC2_F29; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "1.700 ns" { cnt_24:u3|temp[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.900 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC3_F29 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.900 ns; Loc. = LC3_F29; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.100 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC4_F29 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 2.100 ns; Loc. = LC4_F29; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.300 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC5_F29 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 2.300 ns; Loc. = LC5_F29; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.500 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC6_F29 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 2.500 ns; Loc. = LC6_F29; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.700 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 7 COMB LC7_F29 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 2.700 ns; Loc. = LC7_F29; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.900 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 8 COMB LC8_F29 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 2.900 ns; Loc. = LC8_F29; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 3.600 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 9 COMB LC1_F31 2 " "Info: 9: + IC(0.500 ns) + CELL(0.200 ns) = 3.600 ns; Loc. = LC1_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.700 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.800 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 10 COMB LC2_F31 2 " "Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 3.800 ns; Loc. = LC2_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.000 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 11 COMB LC3_F31 2 " "Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 4.000 ns; Loc. = LC3_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.200 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 12 COMB LC4_F31 2 " "Info: 12: + IC(0.000 ns) + CELL(0.200 ns) = 4.200 ns; Loc. = LC4_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.400 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 13 COMB LC5_F31 2 " "Info: 13: + IC(0.000 ns) + CELL(0.200 ns) = 4.400 ns; Loc. = LC5_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.600 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 14 COMB LC6_F31 2 " "Info: 14: + IC(0.000 ns) + CELL(0.200 ns) = 4.600 ns; Loc. = LC6_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.800 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 15 COMB LC7_F31 2 " "Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = LC7_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\] 16 COMB LC8_F31 2 " "Info: 16: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = LC8_F31; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 5.700 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\] 17 COMB LC1_F33 2 " "Info: 17: + IC(0.500 ns) + CELL(0.200 ns) = 5.700 ns; Loc. = LC1_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.700 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.900 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\] 18 COMB LC2_F33 2 " "Info: 18: + IC(0.000 ns) + CELL(0.200 ns) = 5.900 ns; Loc. = LC2_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.100 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\] 19 COMB LC3_F33 2 " "Info: 19: + IC(0.000 ns) + CELL(0.200 ns) = 6.100 ns; Loc. = LC3_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.300 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\] 20 COMB LC4_F33 2 " "Info: 20: + IC(0.000 ns) + CELL(0.200 ns) = 6.300 ns; Loc. = LC4_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.500 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\] 21 COMB LC5_F33 2 " "Info: 21: + IC(0.000 ns) + CELL(0.200 ns) = 6.500 ns; Loc. = LC5_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.700 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\] 22 COMB LC6_F33 2 " "Info: 22: + IC(0.000 ns) + CELL(0.200 ns) = 6.700 ns; Loc. = LC6_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 6.900 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\] 23 COMB LC7_F33 2 " "Info: 23: + IC(0.000 ns) + CELL(0.200 ns) = 6.900 ns; Loc. = LC7_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.100 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\] 24 COMB LC8_F33 2 " "Info: 24: + IC(0.000 ns) + CELL(0.200 ns) = 7.100 ns; Loc. = LC8_F33; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 7.800 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\] 25 COMB LC1_F35 2 " "Info: 25: + IC(0.500 ns) + CELL(0.200 ns) = 7.800 ns; Loc. = LC1_F35; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.700 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.000 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\] 26 COMB LC2_F35 2 " "Info: 26: + IC(0.000 ns) + CELL(0.200 ns) = 8.000 ns; Loc. = LC2_F35; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.200 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\] 27 COMB LC3_F35 2 " "Info: 27: + IC(0.000 ns) + CELL(0.200 ns) = 8.200 ns; Loc. = LC3_F35; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.400 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\] 28 COMB LC4_F35 2 " "Info: 28: + IC(0.000 ns) + CELL(0.200 ns) = 8.400 ns; Loc. = LC4_F35; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.600 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\] 29 COMB LC5_F35 2 " "Info: 29: + IC(0.000 ns) + CELL(0.200 ns) = 8.600 ns; Loc. = LC5_F35; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.800 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\] 30 COMB LC6_F35 2 " "Info: 30: + IC(0.000 ns) + CELL(0.200 ns) = 8.800 ns; Loc. = LC6_F35; Fanout = 2; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.000 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\] 31 COMB LC7_F35 1 " "Info: 31: + IC(0.000 ns) + CELL(0.200 ns) = 9.000 ns; Loc. = LC7_F35; Fanout = 1; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.200 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 10.400 ns cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|unreg_res_node\[31\] 32 COMB LC8_F35 1 " "Info: 32: + IC(0.000 ns) + CELL(1.400 ns) = 10.400 ns; Loc. = LC8_F35; Fanout = 1; COMB Node = 'cnt_24:u3\|lpm_add_sub:add_rtl_1\|addcore:adder\|unreg_res_node\[31\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "1.400 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 12.200 ns cnt_24:u3\|temp\[31\] 33 REG LC3_F34 2 " "Info: 33: + IC(1.000 ns) + CELL(0.800 ns) = 12.200 ns; Loc. = LC3_F34; Fanout = 2; REG Node = 'cnt_24:u3\|temp\[31\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "1.800 ns" { cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] cnt_24:u3|temp[31] } "NODE_NAME" } "" } } { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.700 ns 71.31 % " "Info: Total cell delay = 8.700 ns ( 71.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 28.69 % " "Info: Total interconnect delay = 3.500 ns ( 28.69 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "12.200 ns" { cnt_24:u3|temp[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] cnt_24:u3|temp[31] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.200 ns" { cnt_24:u3|temp[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] cnt_24:u3|temp[31] } { 0.000ns 1.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.400ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 74 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cnt_24:u3\|temp\[31\] 2 REG LC3_F34 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_F34; Fanout = 2; REG Node = 'cnt_24:u3\|temp\[31\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.400 ns" { clk cnt_24:u3|temp[31] } "NODE_NAME" } "" } } { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temp[31] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temp[31] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 74 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cnt_24:u3\|temp\[1\] 2 REG LC8_F30 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_F30; Fanout = 3; REG Node = 'cnt_24:u3\|temp\[1\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.400 ns" { clk cnt_24:u3|temp[1] } "NODE_NAME" } "" } } { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temp[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temp[31] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temp[31] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temp[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "cnt_24.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt_24.vhd" 19 -1 0 } }  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "12.200 ns" { cnt_24:u3|temp[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] cnt_24:u3|temp[31] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.200 ns" { cnt_24:u3|temp[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[9] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[10] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[11] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[12] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[31] cnt_24:u3|temp[31] } { 0.000ns 1.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.400ns 0.800ns } } } { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temp[31] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temp[31] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt_24:u3|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt_24:u3|temp[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "cnt60a:u2\|qh\[0\] en clk 15.000 ns register " "Info: tsu for register \"cnt60a:u2\|qh\[0\]\" (data pin = \"en\", clock pin = \"clk\") is 15.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.800 ns + Longest pin register " "Info: + Longest pin to register delay is 16.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns en 1 PIN PIN_8 17 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 17; PIN Node = 'en'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { en } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(1.600 ns) 11.900 ns cnt60a:u2\|qh~252 2 COMB LC6_F23 1 " "Info: 2: + IC(5.400 ns) + CELL(1.600 ns) = 11.900 ns; Loc. = LC6_F23; Fanout = 1; COMB Node = 'cnt60a:u2\|qh~252'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "7.000 ns" { en cnt60a:u2|qh~252 } "NODE_NAME" } "" } } { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 13.900 ns cnt60a:u2\|qh~253 3 COMB LC1_F23 4 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 13.900 ns; Loc. = LC1_F23; Fanout = 4; COMB Node = 'cnt60a:u2\|qh~253'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.000 ns" { cnt60a:u2|qh~252 cnt60a:u2|qh~253 } "NODE_NAME" } "" } } { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.000 ns) 16.800 ns cnt60a:u2\|qh\[0\] 4 REG LC6_C24 5 " "Info: 4: + IC(1.900 ns) + CELL(1.000 ns) = 16.800 ns; Loc. = LC6_C24; Fanout = 5; REG Node = 'cnt60a:u2\|qh\[0\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.900 ns" { cnt60a:u2|qh~253 cnt60a:u2|qh[0] } "NODE_NAME" } "" } } { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.200 ns 54.76 % " "Info: Total cell delay = 9.200 ns ( 54.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.600 ns 45.24 % " "Info: Total interconnect delay = 7.600 ns ( 45.24 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "16.800 ns" { en cnt60a:u2|qh~252 cnt60a:u2|qh~253 cnt60a:u2|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { en en~out cnt60a:u2|qh~252 cnt60a:u2|qh~253 cnt60a:u2|qh[0] } { 0.000ns 0.000ns 5.400ns 0.300ns 1.900ns } { 0.000ns 4.900ns 1.600ns 1.700ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 74 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/liuwei/VHDL/clk/clock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cnt60a:u2\|qh\[0\] 2 REG LC6_C24 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_C24; Fanout = 5; REG Node = 'cnt60a:u2\|qh\[0\]'" {  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "0.400 ns" { clk cnt60a:u2|qh[0] } "NODE_NAME" } "" } } { "cnt60a.vhd" "" { Text "E:/liuwei/VHDL/clk/cnt60a.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt60a:u2|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt60a:u2|qh[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "16.800 ns" { en cnt60a:u2|qh~252 cnt60a:u2|qh~253 cnt60a:u2|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { en en~out cnt60a:u2|qh~252 cnt60a:u2|qh~253 cnt60a:u2|qh[0] } { 0.000ns 0.000ns 5.400ns 0.300ns 1.900ns } { 0.000ns 4.900ns 1.600ns 1.700ns 1.000ns } } } { "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" "" { Report "E:/liuwei/VHDL/clk/db/cnt_24_cmp.qrpt" Compiler "cnt_24" "UNKNOWN" "V1" "E:/liuwei/VHDL/clk/db/cnt_24.quartus_db" { Floorplan "E:/liuwei/VHDL/clk/" "" "2.400 ns" { clk cnt60a:u2|qh[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cnt60a:u2|qh[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
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