clock.fit.summary

来自「这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Sun Jun 05 16:01:28 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Web Edition
Revision Name : clock
Top-level Entity Name : clock
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 161 / 1,728 ( 9 % )
Total pins : 33 / 102 ( 32 % )
Total memory bits : 0 / 24,576 ( 0 % )
Total PLLs : 0