cnt_24.tan.rpt

来自「这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以」· RPT 代码 · 共 279 行 · 第 1/5 页

Timing Analyzer report for cnt_24
Sun Jun 05 15:07:33 2005
Version 5.0 Build 148 04/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                  ;
+------------------------------+-------+---------------+----------------------------------+--------------------+--------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From               ; To                 ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------------+--------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 15.000 ns                        ; en                 ; cnt60a:u2|qh[3]    ;            ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 11.300 ns                        ; cnt_24:u3|temph[3] ; q3h[3]             ; clk        ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.100 ns                        ; m_set              ; cnt60a:u2|ql[2]    ;            ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 75.19 MHz ( period = 13.300 ns ) ; cnt_24:u3|temp[1]  ; cnt_24:u3|temp[31] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                    ;                    ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------+--------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;