📄 cnt_24.map.rpt
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; Total registers ; 71 ;
; Total logic cells in carry chains ; 36 ;
; I/O pins ; 33 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 71 ;
; Total fan-out ; 554 ;
; Average fan-out ; 3.01 ;
+-----------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------+
; |clock ; 151 (4) ; 71 ; 0 ; 33 ; 80 (4) ; 38 (0) ; 33 (0) ; 36 (0) ; |clock ;
; |cnt60a:u1| ; 30 (30) ; 16 ; 0 ; 0 ; 14 (14) ; 6 (6) ; 10 (10) ; 0 (0) ; |clock|cnt60a:u1 ;
; |cnt60a:u2| ; 28 (28) ; 15 ; 0 ; 0 ; 13 (13) ; 5 (5) ; 10 (10) ; 0 (0) ; |clock|cnt60a:u2 ;
; |cnt_24:u3| ; 89 (51) ; 40 ; 0 ; 0 ; 49 (15) ; 27 (27) ; 13 (9) ; 36 (1) ; |clock|cnt_24:u3 ;
; |lpm_add_sub:add_rtl_1| ; 31 (0) ; 0 ; 0 ; 0 ; 31 (0) ; 0 (0) ; 0 (0) ; 31 (0) ; |clock|cnt_24:u3|lpm_add_sub:add_rtl_1 ;
; |addcore:adder| ; 31 (1) ; 0 ; 0 ; 0 ; 31 (1) ; 0 (0) ; 0 (0) ; 31 (1) ; |clock|cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder ;
; |a_csnbuffer:result_node| ; 30 (30) ; 0 ; 0 ; 0 ; 30 (30) ; 0 (0) ; 0 (0) ; 30 (30) ; |clock|cnt_24:u3|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node ;
; |lpm_counter:templ_rtl_0| ; 7 (0) ; 4 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |clock|cnt_24:u3|lpm_counter:templ_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 4 (4) ; |clock|cnt_24:u3|lpm_counter:templ_rtl_0|alt_counter_f10ke:wysi_counter ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 71 ;
; Number of registers using Synchronous Clear ; 4 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 24 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 71 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: cnt_24:u3|lpm_counter:templ_rtl_0 ;
+------------------------+---------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+---------+-------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+---------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: cnt_24:u3|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+-------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-------------------------------------------+
; LPM_WIDTH ; 32 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_5nh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/liuwei/VHDL/clk/cnt_24.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
Info: Processing started: Sun Jun 05 15:07:06 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt_24 -c cnt_24
Info: Found 2 design units, including 1 entities, in source file cnt_24.vhd
Info: Found design unit 1: cnt_24-one
Info: Found entity 1: cnt_24
Info: Using design file clock.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: clock-behv
Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at clock.vhd(23): object "cy1" declared but not used
Info: (10035) Verilog HDL or VHDL information at clock.vhd(23): object "cy2" declared but not used
Info: Using design file cnt60a.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: cnt60a-one
Info: Found entity 1: cnt60a
Info: Elaborating entity "cnt60a" for hierarchy "cnt60a:u1"
Info: Elaborating entity "cnt_24" for hierarchy "cnt_24:u3"
Info: (10035) Verilog HDL or VHDL information at cnt_24.vhd(20): object "cq" declared but not used
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt_24:u3|templ[0]~51"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
Info: Duplicate register "cnt60a:u2|\p1:templ[0]" merged to single register "cnt60a:u1|\p1:templ[0]"
Info: Implemented 184 device resources after synthesis - the final resource count might be different
Info: Implemented 9 input pins
Info: Implemented 24 output pins
Info: Implemented 151 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jun 05 15:07:11 2005
Info: Elapsed time: 00:00:05
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