cnt_24.fit.talkback.xml

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!

		<pin__>41</pin__>
		<col.>31</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q1h[1]</name>
		<pin__>138</pin__>
		<col.>31</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q1h[2]</name>
		<pin__>140</pin__>
		<col.>32</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q1h[3]</name>
		<pin__>32</pin__>
		<row>F</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2l[0]</name>
		<pin__>116</pin__>
		<col.>7</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2l[1]</name>
		<pin__>79</pin__>
		<row>F</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2l[2]</name>
		<pin__>81</pin__>
		<row>F</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2l[3]</name>
		<pin__>117</pin__>
		<col.>8</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2h[0]</name>
		<pin__>18</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2h[1]</name>
		<pin__>12</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2h[2]</name>
		<pin__>13</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q2h[3]</name>
		<pin__>95</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3l[0]</name>
		<pin__>51</pin__>
		<col.>20</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3l[1]</name>
		<pin__>128</pin__>
		<col.>19</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3l[2]</name>
		<pin__>31</pin__>
		<row>F</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3l[3]</name>
		<pin__>80</pin__>
		<row>F</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3h[0]</name>
		<pin__>33</pin__>
		<row>F</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3h[1]</name>
		<pin__>78</pin__>
		<row>F</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3h[2]</name>
		<pin__>47</pin__>
		<col.>25</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q3h[3]</name>
		<pin__>20</pin__>
		<row>D</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
</output_pins>
<compilation_summary>
	<flow_status>Successful - Sun Jun 05 15:07:27 2005</flow_status>
	<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>cnt_24</revision_name>
	<top_level_entity_name>clock</top_level_entity_name>
	<family>ACEX1K</family>
	<device>EP1K30TC144-3</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>151 / 1,728 ( 8 % )</total_logic_elements>
	<total_pins>33 / 102 ( 32 % )</total_pins>
	<total_memory_bits>0 / 24,576 ( 0 % )</total_memory_bits>
	<total_plls>0</total_plls>
</compilation_summary>
<compile_id>E988C328</compile_id>
<files>
	<top>E:/liuwei/VHDL/clk/clock.vhd</top>
	<extensions>
		<ext ext_name="vhd">3</ext>
		<ext ext_name="tdf">6</ext>
		<ext ext_name="inc">20</ext>
		<ext ext_name="lst">1</ext>
	</extensions>
	<sub_files>
		<sub_file>E:/liuwei/VHDL/clk/cnt_24.vhd</sub_file>
		<sub_file>E:/liuwei/VHDL/clk/clock.vhd</sub_file>
		<sub_file>E:/liuwei/VHDL/clk/cnt60a.vhd</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_constant.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_decode.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/cmpconst.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_compare.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_counter.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/dffeea.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/alt_synch_counter.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/alt_synch_counter_f.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/aglobal50.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/cbx.lst</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/flex10ke_lcell.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/addcore.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/look_add.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/bypassff.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altshift.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/alt_stratix_add_sub.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/alt_mercury_add_sub.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/addcore.tdf</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altshift.tdf</sub_file>
	</sub_files>
</files>
<architecture>
	<family>ACEX1K</family>
	<auto_device>OFF</auto_device>
	<device>EP1K30TC144-3</device>
</architecture>
<pkg_io>
	<pin_std count="33">LVTTL/LVCMOS</pin_std>
</pkg_io>
</talkback>