📄 receive.rpt
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clock_div_1 ........XX.XXXX......................... 6 6
sbuf<7> XXXXXXXX.......XXXXXX................... 14 14
clock_div_2 ........XXXXXXX......................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 57 I/O
(unused) 0 0 0 5 FB4_3 58 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 61 I/O
(unused) 0 0 0 5 FB4_6 62 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O
(unused) 0 0 0 5 FB4_9 65 I/O
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 66 I/O
(unused) 0 0 0 5 FB4_12 67 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 68 I/O
(unused) 0 0 0 5 FB4_15 69 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 70 I/O
(unused) 0 0 0 5 FB4_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 20/16
Number of signals used by logic mapping into function block: 20
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/4 1 FB5_1 (b) (b)
sbuf<6> 7 4<- \/2 0 FB5_2 STD 32 I/O O
sbuf<5> 7 2<- 0 0 FB5_3 STD 33 I/O O
(unused) 0 0 \/4 1 FB5_4 (b) (b)
sbuf<4> 7 4<- \/2 0 FB5_5 STD 34 I/O O
sbuf<3> 7 2<- 0 0 FB5_6 STD 35 I/O O
bit_cnt_3 3 0 \/2 0 FB5_7 STD (b) (b)
sbuf<2> 7 2<- 0 0 FB5_8 STD 36 I/O O
sbuf<1> 7 2<- 0 0 FB5_9 STD 37 I/O O
bit_cnt_2 3 0 /\2 0 FB5_10 STD (b) (b)
sbuf<0> 7 2<- 0 0 FB5_11 STD 39 I/O O
bit_cnt_1 3 0 /\2 0 FB5_12 STD 40 I/O (b)
bit_cnt_0 3 0 \/2 0 FB5_13 STD (b) (b)
count_reg_1 4 2<- \/3 0 FB5_14 STD 41 I/O (b)
count_reg_0 4 3<- \/4 0 FB5_15 STD 43 I/O (b)
rxd_start_reg 13 8<- 0 0 FB5_16 STD (b) (b)
bit_collect_1 3 2<- /\4 0 FB5_17 STD 44 I/O (b)
bit_collect_0 3 0 /\2 0 FB5_18 STD (b) (b)
Signals Used by Logic in Function Block
1: N106.FBK.LFBK 8: rxd 15: clock_pluse
2: N109.FBK.LFBK 9: bit_cnt_0.FBK.LFBK
16: count_reg_0.FBK.LFBK
3: N112.FBK.LFBK 10: bit_cnt_1.FBK.LFBK
17: count_reg_1.FBK.LFBK
4: N115.FBK.LFBK 11: bit_cnt_2.FBK.LFBK
18: count_reg_2
5: N118.FBK.LFBK 12: bit_cnt_3.FBK.LFBK
19: count_reg_3
6: N121.FBK.LFBK 13: bit_collect_0.FBK.LFBK
20: rxd_start_reg.FBK.LFBK
7: N124.FBK.LFBK 14: bit_collect_1.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
sbuf<6> ......XXXXXXXXXXXXXX.................... 14 14
sbuf<5> .....X.XXXXXXXXXXXXX.................... 14 14
sbuf<4> ....X..XXXXXXXXXXXXX.................... 14 14
sbuf<3> ...X...XXXXXXXXXXXXX.................... 14 14
bit_cnt_3 .......XXXXX..XXXXXX.................... 11 11
sbuf<2> ..X....XXXXXXXXXXXXX.................... 14 14
sbuf<1> .X.....XXXXXXXXXXXXX.................... 14 14
bit_cnt_2 .......XXXX...XXXXXX.................... 10 10
sbuf<0> X......XXXXXXXXXXXXX.................... 14 14
bit_cnt_1 .......XXX....XXXXXX.................... 9 9
bit_cnt_0 .......XX.....XXXXXX.................... 8 8
count_reg_1 .......X......XXXXXX.................... 7 7
count_reg_0 .......X......XXXXXX.................... 7 7
rxd_start_reg .......XXXXXXXXXXXXX.................... 13 13
bit_collect_1 .......X.....XXXXXXX.................... 8 8
bit_collect_0 .......X....X.XXXXXX.................... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 45 I/O
(unused) 0 0 0 5 FB6_3 46 I/O
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 47 I/O
(unused) 0 0 0 5 FB6_6 48 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 50 I/O
(unused) 0 0 0 5 FB6_9 51 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 52 I/O
(unused) 0 0 0 5 FB6_12 53 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 54 I/O
(unused) 0 0 0 5 FB6_15 55 I/O
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 56 I/O
(unused) 0 0 0 5 FB6_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"sbuf<0>".T = rxd * count_reg_2 * /count_reg_3 *
bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK *
count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N106.FBK.LFBK
+ rxd * count_reg_2 * /count_reg_3 *
bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK *
bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N106.FBK.LFBK
+ /rxd * count_reg_2 * /count_reg_3 *
bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK *
count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK
+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK *
/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK *
count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK *
bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N106.FBK.LFBK
;Imported pterms FB5_12
+ /rxd * count_reg_2 * /count_reg_3 *
bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK *
/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK
+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK *
/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK *
count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK *
/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK
"sbuf<0>".CLKF = clock_pluse
"sbuf<0>".PRLD = VCC
"sbuf<1>".T = rxd * count_reg_2 * /count_reg_3 *
/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK *
count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N109.FBK.LFBK
+ rxd * count_reg_2 * /count_reg_3 *
/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK *
bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N109.FBK.LFBK
+ /rxd * count_reg_2 * /count_reg_3 *
/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK *
count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N109.FBK.LFBK
+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK *
bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK *
count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK *
bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N109.FBK.LFBK
;Imported pterms FB5_10
+ /rxd * count_reg_2 * /count_reg_3 *
/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK *
/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N109.FBK.LFBK
+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK *
bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK *
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