send.syr

结合XILINXCPLD所做的模拟RS232通信verilog源程序

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : send.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : send
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : send
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : send.prj
Compiling included source file 'send.v'
Module <send> compiled.
Continuing compilation of source file 'send.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'send.prj'
No errors in compilation
Analysis of file <send.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <send>.
Module <send> is correct for synthesis.

Synthesizing Unit <send>.
    Related source file is send.v.
WARNING:Xst:737 - Found 8-bit latch for signal <uart_buf>.
    Found 11-bit comparator less for signal <$n0001> created at line 16.
    Found 4-bit comparator less for signal <$n0006> created at line 52.
    Found 4-bit adder for signal <$n0017> created at line 53.
    Found 1-bit register for signal <bit_start>.
    Found 4-bit register for signal <bitcnt_reg>.
    Found 11-bit up counter for signal <count>.
    Found 1-bit register for signal <txd_reg>.
    Summary:
	inferred   1 Counter(s).
	inferred   6 D-type flip-flop(s).
	inferred   8 Latch(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <send> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 3
  4-bit register                   : 1
  1-bit register                   : 2
# Latches                          : 1
  8-bit latch                      : 1
# Counters                         : 1
  11-bit up counter                : 1
# Adders/Subtractors               : 1
  4-bit adder                      : 1
# Comparators                      : 2
  11-bit comparator less           : 1
  4-bit comparator less            : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <send> ...
=========================================================================
Final Results
Output File Name                   : send
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Comparators                      : 2
  11-bit comparator less           : 1
  4-bit comparator less            : 1
# Xors                             : 13
  1-bit xor2                       : 13

Design Statistics
# Edif Instances                   : 147
# I/Os                             : 10

=========================================================================
CPU : 2.25 / 2.41 s | Elapsed : 2.00 / 2.00 s
 
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